1. Technical Field
The present invention relates generally to a semiconductor integrated circuit such as IC and LSI and particularly to a semiconductor integrated circuit that operates upon supply of a plurality of power potentials.
2. Related Art
In order to realize high-speed and low-electricity operation of various types of electronic apparatuses such as an IC and an LSI, semiconductor integrated circuits used in these electronic apparatuses are becoming more highly integrated and operating on more reduced voltages. However, it is extremely difficult to reduce operation voltages in all semiconductor integrated circuits in view of device-specific characteristics. Therefore, a situation occurs in which a plurality of semiconductor integrated circuits that operate on different power potentials become coupled to each other.
To cope with such a situation, a semiconductor integrated circuit having an internal circuit that operates upon supply of a low power potential and an output circuit that operates upon supply of a high power potential has been developed. An example of such a semiconductor integrated circuit operating upon supply of two kinds of power potentials will be explained with reference to FIG. 6.
The semiconductor integrated circuit shown in FIG. 6 contains: an internal circuit 10 that operates upon supply of a first power potential LVDD (e.g., 1.8V); an inverter 20 that inverts an output signal of the internal circuit 10 upon supply of the first power potential LVDD; a level shift circuit 30, which inputs the output signal of the internal circuit 10 into a first input terminal (a node A) while inputting the output signal of the inverter 20 into a second input terminal (a node B), which generates, upon supply of the second power potential HVDD (e.g., 3.3V) and at each of first and second output terminals (nodes C and D), the input level shift signal whose level has been shifted, and which outputs the level shift signal from the second output terminal (the node D); and an output circuit (an inverter 40 in this case) that operates upon supply of the second power potential LVDD.
The level shift circuit 30 is composed of: a P-channel MOS transistor QP1 and an N-channel MOS transistor QN1 connected in series, whose gates receive the output signal of the internal circuit 10; a P-channel MOS transistor QP2 and an N-channel MOS transistor QN2 connected in series, whose gates receive the output signal of the inverter 20; a P-channel MOS transistor QP3 that supplies current to the transistors QP1 and QN1; and a fourth P-channel MOS transistor QP4 that supplies current to the transistors QP2 and QN2.
By shifting the level of the input signal, the level shift circuit 30 generates the level shift signal having a level suitable for the inverter 40 that operates upon supply of the power potential HVDD. After being inverted by the inverter 40, this level shift signal is supplied via an output pad to an external circuit that operates on the power potential HVDD or higher than the power potential HVDD.
With such a semiconductor integrated circuit, there is a case in which the second power potential HVDD is supplied even when the first power potential LVDD is not supplied for a reason such as that the external circuit connected to the output pad is operating. In such a case, an output of the internal circuit 10 and the inverter 20 becomes a high impedance state (the potential is unstable), and a through current I1 may flow via the transistors QP3, QP1, and QN1 depending on the potentials of the nodes A and B. Further, depending on the potentials of the nodes A and B, a through current I2 may flow via the transistors QP4, QP2, and QN2.
As a related technique, JP-A-06-236693 discloses a device for protecting an integrated circuit so that random storage and erase of data is prevented from unwanted or unexpected cut off of power. This device is equipped with: a voltage source that generates a programming/erasure voltage Vpp; cut-off means connected in series between the voltage source and a supply input of the integrated circuit corresponding to this voltage source; and means to activate the cut-off means, connected to the voltage source that generates a normal supply voltage Vcc. This cut-off means is activated when the voltage Vcc falls below a certain threshold voltage and protects the data from being rewritten or erased. However, JP-A-06-236693 does not mention on prevention against the through current flowing to the level shift circuit when only one out of the two kinds of power potentials is being supplied.